1. Field of the Invention
The present invention relates to a flat panel display device comprising a polysilicon thin film transistor and a method of manufacturing the same. More particularly, it relates to a flat panel display device comprising polysilicon thin film transistors having different sizes and shapes of polysilicon grains formed in an active channel region of a thin film transistor.
2. Discussion of the Related Art
Bonding defects such as dangling bonds exist at grain boundaries of the polysilicon used in active channel regions of thin film transistors (TFTs). These defects have been known to act as traps for electric charge carriers.
TFT characteristics such as threshold voltage (Vth), subthreshold slope, charge carrier mobility, leakage current, device stability, and the like are affected either directly or indirectly by the size, uniformity, number, position and direction of the grains and/or grain boundaries in the channel region of TFTs. For example, the position of the grains is also capable of affecting either directly or indirectly the uniformity of the TFTs manufactured for an active matrix display.
Currently the number of grain boundaries (which may be referred to as “primary” grain boundaries) that are included in the active channel region of the TFTs over an entire substrate may be equal to or different from each other. Referring to FIGS. 1A and 1B, this number depends on the size of the grains, slope angle θ, dimensions of the active channel region (e.g., length L, width W), and position of each TFT on the substrate.
As shown in FIGS. 1A and 1B, the number of primary grain boundaries capable of being included in the active channel region may be represented as Nmax. This number depends on the grain sizes (Gs), the active channel dimensions (L×W), the slope angle (θ), and on the position on the TFT substrate. The maximum number of primary grain boundaries is Nmax, and is 3, in the case of FIG. 1A. In the case of FIG. 1B the maximum number of primary grain boundaries becomes Nmax−1, and is 2.
Excellent TFT characteristics can be obtained when TFTs included in the active channel regions over the substrate have the Nmax number of primary grain boundaries. The uniformity of the device increases as the number of TFTs having an equal number of the grain boundaries can be obtained.
In contrast, when the number of the TFT comprising a Nmax number of the primary grain boundaries is equal to the number of the TFT comprising Nmax−1 of primary grain boundaries, the uniformity is worse.
In this regard, sequential lateral solidification (SLS) crystallization technology is capable of forming large silicon grains of polycrystalline or single crystal particles on the substrate as shown in FIG. 2A and FIG. 2B. It has been reported that TFTs manufactured using SLS crystallization technology have similar characteristics to TFTs manufactured with single crystals.
Numerous TFTs for driver and pixel arrays are needed in the manufacture of an active matrix display. For example, an active matrix display having a SVGA resolution level may be manufactured with about one million pixels. Also, when using a liquid crystal display (LCD) each pixel requires one TFT and when using an organic luminescent material (e.g., organic electroluminescent device) each pixel requires at least two TFTs. Therefore, one million or two million TFTs may be required in the active matrix display. Accordingly, due to the large number of required TFTs it is impossible to have uniform number of grains grown and manufactured in the uniform directions in the active channel regions for each of these TFTs.
U.S. Pat. No. 6,322,625 discloses technology for converting amorphous silicon into polysilicon. This patent is incorporated by reference as if fully set forth herein. Additionally, the reference discloses crystallizing selected regions on the substrate by using SLS technology. The amorphous silicon may be deposited with plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sputtering techniques, or the like.
Referring to FIG. 2A and FIG. 2B, the selected region for crystallization may be substantially wide region when compared with the active channel region. That is, the selected region may be several μms by several μms. Additionally, a laser used in the crystallization technology may have a beam area of several mm by several tens of mm. The laser may use a stepper or a stage for shifting the laser beam in order to crystallize the amorphous silicon in the entire region or a selected region on the substrate.
Misalignment of the laser beam during operation, for example, misalignment between regions during irradiation may cause misalignment in the active channel regions of the numerous TFTs. As a result a number of the grain boundaries may be different in the various TFTs over the entire substrate or in the driver and pixel cell regions, thereby creating unpredictable characteristics. These non-uniformities may exert a negative influence on the active matrix display device.
U.S. Pat. No. 6,177,391 is hereby incorporated by reference as if fully set forth herein. As in U.S. Pat. No. 6,177,391 and referring to FIG. 3A, when the direction of an active channel is parallel with a grain direction grown by SLS crystallization a barrier effect of the grain boundaries with respect to the direction of an electric charge carrier is minimized. As a result, TFT characteristics similar to single crystal silicon can be obtained. Referring to FIG. 3B, when the active channel direction and the grain direction constitute about a 90° angle a number of the grain boundaries act as traps for electric charge carriers and the TFT characteristics are remarkably lowered.
Typically the active channel direction and the grain direction of TFTs in a driver circuit and the TFTs in a pixel cell region may have a 90° angle when the active matrix display is manufactured. Referring to FIG. 3C, in order to improve the uniformity characteristics between TFTs and without largely decreasing the characteristics of each TFT the direction of the active channel region with respect to the grain growth direction is manufactured with an inclined slope of about 30° to 90°. As a result, the uniformity of the device may be increased.
This method, however, has a possibility of having primary grain boundaries in the active channel region by using a limited size of grain formed by the SLS crystallization technology. Thus, a problem of unpredictability with non-uniformities exists and causes different characteristics among the TFTs.
Additionally, the display device may employ complementary metal oxide semiconductor (CMOS) thin film transistor (TFT) in the circuits. Generally, an absolute value of the threshold voltage of the TFT is larger than that of a MOS transistor using the single-crystal semiconductor. Also, the absolute value of a threshold voltage of an N-type TFT is substantially different from the absolute value of a P-type TFT. For example, when the threshold voltage of the N-type TFT is 2V the threshold voltage of the P-type TFT is −4V.
Therefore, these substantial differences between the absolute values of the threshold voltages of the P-type TFT and the N-type TFT exert negative influences on the operation of the circuit, especially, by acting as a large obstacle in decreasing a driving voltage. For example, generally a P-type TFT has a large absolute threshold voltage value and is not suitably operated at low driving voltages. That is, the P-type TFT functions as a passive device at low driving voltages such as a register and is not operated properly. A substantially high voltage is required in order to properly operate the P-type TFT as the active device.
This may be exaggerated as work functions between the gate electrode and the intrinsic silicon are different. For example, the gate electrode may be of aluminum and has a work function below 5 eV. As the work functions between the gate electrode and an intrinsic silicon semiconductor become smaller such as −0.6 eV the threshold voltage of the P-type TFT approaches a negative value and the threshold voltage of the N-type TFT approaches 0 V. Accordingly, the N-type TFT may shift to an “on” state of operation.
In the state as described above, the absolute values of the threshold voltages of the N-type TFT and the P-type TFT are preferably substantially equal to each other. In the case of a conventional single-crystal semiconductor integrated circuit technology, the threshold voltage may be controlled using N-type or P-type impurities. That is, these impurities may be doped into the semiconductor at very low concentrations of about or below 1018 atom/cm2. Accordingly, the threshold voltages are precisely controlled below 0.1V by the impurity doping of 1015 to 1018 atom/cm2 concentration.
In contrast, when using a semiconductor that are not a single-crystal semiconductor, the shift of the threshold voltages is not observed by adding impurities with a concentration of about or below 1018 atom/cm2. In addition, when the concentration of the impurities is higher than 1018 atom/cm2 the threshold voltage is rapidly varied and conductivity becomes a P-type or an N-type as the polycrystalline silicon contains many defects. Since a defect concentration is 1018 atom/cm2, the added impurities cannot be trapped and/or activated by this defect. Furthermore, the concentration of the impurities is larger than that of the defects, and excess impurities are activated that may cause the conductivity type to be varied from an N-type or P-type.
The related art tries to solve these problems, for example, in U.S. Pat. Nos. 6,492,268, 6,124,603 and 5,615,935, by providing shorter channel lengths of the P-type TFTs than the channel lengths of the N-type TFTs. These patents cited herein are incorporated by reference herein in their entirety. However, these patents also create problems by complicating the manufacturing process since the channel lengths are manufactured with different lengths from each other.